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| Ordering number : EN*5536A CMOS LSI LC89170M CD Player Text Data IC Preliminary Overview The LC89170M is an IC that decodes the text data, such as song names, stored in subcode channels R to W of a compact disk's read-in area. Package Dimensions unit: mm 3111-MFP14S [LC89170M] Features * Accepts the channel R to W subcode data through a subcode interface. * Can continuously output the channel R to W data for each 1PACK24 symbol. * Performs error detection (cyclic redundancy code) and outputs both the data and the result of that check. * Provides synchronization protection for the subcode interface. * Supports low-voltage operation (3.3 V) * Provided in the miniature MFP-14S package. SANYO: MFP14S Specifications Absolute Maximum Ratings at Ta = 25 C, VSS = 0 V Parameter Maximum supply voltage I/O voltages Input current Operating temperature Storage temperature Symbol VDD max VI VO II Topr Tstg Conditions Ratings -0.3 to +7.0 -0.3 to VDD + 0.3 10 -30 to +70 -55 to +125 Unit V V mA C C Recommended Operating Conditions at Ta = 25 C, VSS = 0 V Parameter Supply voltage Operating temperature Symbol VDD Topr Conditions Ratings min 3.0 -30 typ 5.0 max 5.5 +70 Unit V V SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 93096HA (OT) No. 5536-1/8 LC89170M Block Diagram Pin Assignment Pin Functions Pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Symbol EXCK SBSO SCOR WFCK MCK XMODE GND TEST SW1 SW2 SCLK SRDT DQSY VDD I I I I O O I/O I/O I I I I I Subcode interface shift clock input and output Subcode interface data input Subcode interface block synchronization input Subcode interface frame synchronization input Clock input (16.9344 MHz) System reset and low power mode Ground Test pin (Must be connected to ground in normal operation.) EXCK I/O setting (L: clock output, H: clock input) EXCK clock output pulse width selection (L: double speed support, H: normal speed) Command interface shift clock input Command interface data output Command interface readout enable output Power supply Function No. 5536-2/8 LC89170M DC Characteristics DC Characteristics (1) at Ta = -30 to +70C, VDD = 4.5 to 5.5 V, VSS = 0 V Parameter Symbol CMOS compatible; 1* CMOS compatible Schmitt; 2* CMOS compatible; 1* CMOS compatible Schmitt; 2* IOH = -2 mA; 3* IOH = 2 mA; 3* VDD = 5 V, Ta = 25C, MCK = 16.93 MHz VDD = 5 V, XMODE = [L] 0.8 60 VDD-2.1 0.4 1.6 120 Conditions Ratings min 0.7 VDD 0.8 VDD 0.3 VDD 0.2 VDD typ max Unit V V V V V V mA A Input high-level voltage VIH VIL VOH VOL IDD Input low-level voltage Output high-level voltage Output low-level voltage Current drain Note: 1. The MCK, TEST, SW1, and SW2 pins 2. The EXCK, SBSO, SCOR, WFCK, XMODE, and SCLK pins 3. The EXCK, SRDT, and DQSY pins DC Characteristics (2) at Ta = -30 to +70C, VDD = 3.0 to 3.6 V, VSS = 0 V Parameter Symbol CMOS compatible; 1* CMOS compatible Schmitt; 2* CMOS compatible; 1* CMOS compatible Schmitt; 2* IOH = -1 mA; 3* IOH = 1 mA; 3* VDD = 3.3 V, Ta = 25C, MCK = 16.93 MHz VDD = 3.3 V, XMODE = [L] 0.5 25 VDD-0.8 0.4 1.0 50 Conditions Ratings min 0.7 VDD 0.75 VDD 0.2 VDD 0.15 VDD typ max Unit V V V V V V mA A Input high-level voltage VIH VIL VOH VOL IDD Input low-level voltage Output high-level voltage Output low-level voltage Current drain Note: 1. The MCK, TEST, SW1, and SW2 pins 2. The EXCK, SBSO, SCOR, WFCK, XMODE, and SCLK pins 3. The EXCK, SRDT, and DQSY pins AC Characteristics * The MCK pin AC Characteristics (1) at Ta = -30 to +70C, VDD = 3.0 to 5.5 V, VSS = 0 V Parameter High-level pulse width Low-level pulse width Pulse period Rise and fall times Symbol tWH tWL tC tR, tF Conditions Ratings min 25 25 58 typ max 56 56 100 12 Unit ns ns ns ns No. 5536-3/8 LC89170M * The SCOR and WFCK pins AC Characteristics (2) at Ta = -30 to +70C, VDD = 3.0 to 5.5 V Parameter Subcode block period Subcode frame period Subcode block synchronization pulse width Subcode frame synchronization High-level pulse width pulse width Low-level pulse width Symbol TB TF TBW tHW tLW Conditions Ratings min 6.0 60 60 4.0 1.5 68 68 typ 13.3 136 max 14.7 150 300 Unit ms s s s s * The EXCK and SBSO pins AC Characteristics (3) at Ta = -30 to +70C, VDD = 3.0 to 5.5 V Parameter Symbol tHPW tHPW tLPW tLPW tCD tCD tRX, tFX tPAC tHD 0 3 Conditions [SW1] = [L] [SW1] = [H] [SW1] = [L] [SW1] = [H] [SW1] = [L] [SW1] = [H] Ratings min 0.9 2 0.9 2 10 0.4 30 10 4 4 typ max 6.4 6 6.4 6 32 Unit s s s s s s s s s High-level pulse width Synchronization clock pulse width Low-level pulse width Shift clock delay time Shift clock rise and fall times P data access time Data hold time * The SCLK, SRDT, and DQSY pins AC Characteristics (4) at Ta = -30 to +70C, VDD = 3.0 to 5.5 V Parameter Readout period DQSY pulse width SCLK low-level pulse width SCLK high-level pulse width SCLK delay time Data delay time Data delay time Symbol tCW tW tWL tWH tD1 tD2 tD3 Conditions Ratings min 1.5 60 100 100 100 50 50 typ 3.3 136 max 3.7 150 Unit ms s ns ns ns ns ns No. 5536-4/8 LC89170M Functional Description * Subcode interface The LC89170M accepts subcode data from the DSP using the EXCK, SBSO, SCOR, and WFCK pins. Figure 1 shows the timing. Figure 1 Subcode Interface Timing SW1 sets the input or output state for the EXCK pin. This pin is provided for cases where a subcode interface shift clock source, such as a CD-G decoder circuit, is present in the vicinity of the LC89170M. Figure 2 shows usage examples. Figure 2 SW1 Usage Examples The SW2 is selected according to the subcode block period, TB, input to the SCOR pin. SW2 Selection SW2 [L] [H] Function Supports up to double speed playback Only supports normal-speed playback TB 6.65 13.3 Unit ms ms No. 5536-5/8 LC89170M The EXCK clock characteristics are determined by SW2 as listed in the table below. EXCK Clock Selection by SW2 SW1 [L] SW2 [L] tCD 12.28 208TMCK 18.90 320TMCK tWH 1.89 32TMCK 7.56 128TMCK tWL 1.89 32TMCK 7.56 128TMCK Unit s s s s [L] [H] The upper boxes assume MCK = 16.934 MHz The lower boxes indicate the relationship with MCK (TMCK = 1/MCK) * Microcontroller interface The LC89170M includes a 32-word x 8-bit dual-port RAM on chip, and the 1PACK 24 symbols from subcode channels R to W can be read out once every 3.3 ms (or once every 1.66 for double-speed playback) over the microcontroller interface. Figure 3 shows the timing. Figure 3 Microcontroller Interface Output Timing The 1PACK 24 symbols for the subcode R to W data (18 bytes) are entered into the dual-port RAM and input to the CRC checking circuit. After the data for 1 PACK has all been input, a falling edge is output from the DQSY pin and the CRC flags are output from SRDT. A high is output for the CRC flags if the check returned OK. Next, 128 bits of data are output by inputting the SCLK clock signal. A single packet of data is output by repeating this operation four times. No. 5536-6/8 LC89170M * Synchronizing signal interpolation and protection Although the LC89170M receives data from the DSP over the subcode interface, it is possible that due to reasons such as defects or damage to the disk, errors may occur in the synchronization pattern (SO, SI) making the LC89170M unable to detect that synchronization pattern, or a signal that is not a synchronizing signal (SCOR) may be recognized as a synchronizing signal making the LC89170M unable to correctly read out the data. The LC89170M includes a synchronizing signal interpolation and protection circuit to handle these problems. Figure 4 describes this interpolation and protection circuit. Although the interpolation circuit generates a synchronization signal for each packet, if the synchronizing signal is missing, it resets on the next detected synchronizing signal and once again generates a synchronizing signal for each packet. (1) In the protection circuit, when a synchronizing signal is detected, if that synchronizing signal does not meet the stipulated period (98 x WFCK) with respect to the previously detected synchronizing signal, the protection circuit has the LC89170M ignore that detected synchronizing signal. This prevents signals that are not synchronizing signals from being mistakenly recognized as synchronizing signals. (2) The processing performed by these circuit is reflected in the CRC flags. Figure 4 Synchronizing Signal Interpolation and Protection At the point marked (1) in the figure, an external SCOR that differs from the interpolated was detected, and here the interpolation circuit is synchronized with this signal. At the point marked (2) in the figure, an external SCOR that differs from the interpolated was detected, but this external SCOR will be ignored and the interpolation circuit will not be re-synchronized. * System reset and low power mode The XMODE pin functions to reset the system and to switch to low power mode. System operation can be started correctly by applying a high level to this pin after the power-supply voltage has risen above 4.5 V (or 3.0 V). Setting the XMODE pin low switches the LC89170M to low power mode. Application Circuit Example No. 5536-7/8 LC89170M s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of September, 1996. Specifications and information herein are subject to change without notice. No. 5536-8/8 |
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